The inventive concept relates to a memory management unit (MMU), and more particularly, to a memory management unit capable of hiding misses during the translation of virtual addresses into physical addresses The inventive concept is also related to apparatuses including this type of MMU.
Memory management units (MMUs) are components used to process memory access operations, such as the type requested by a direct memory access unit of a central processing unit (CPU). The MMU may be called a paged memory management unit (PMMU).
When the MMU has a multi-channel bus interface, various problems may be generated in the MMU due to a channel misses. For example, when the translation of a virtual address to a corresponding physical address misses for a particular channel of the MMU, a virtual address output from another channel must wait until the miss is correctly processed. It is desirable during operation of a MMU to reduce the time required to handle or further process a miss, thereby reducing the so-called miss penalty.